• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring of semiconductor devices, and more particularly, to a method of forming a wiring of a semiconductor device suitable for minimizing heat dissipation effect and hillock generation due to an increase in surface area of wiring lines. In the method for forming a wiring of a semiconductor device according to the present invention, the method includes forming a first insulating film on a semiconductor substrate, forming a trench having a demesin structure on the first insulating film, and contacting metal on the entire surface of the first insulating film including the trench. And forming an anti-reflection film on the adhesion metal along the trench and the first insulating film surface along the trench and the surface of the first insulating film, and polishing the anti-reflection film, the wiring layer and the adhesion metal to expose the upper surface of the first insulating film. And forming a second insulating film over the entire wiring layer including the first insulating film, thereby effectively dissipating heat generated from the wiring layer to prevent electromigration and to suppress the occurrence of hillock. It can work.
    公开号:KR19980052473A
    申请号:KR1019960071462
    申请日:1996-12-24
    公开日:1998-09-25
    发明作者:권태석
    申请人:문정환；엘지반도체 주식회사；
    IPC主号:
    专利说明:

    Wiring Formation Method of Semiconductor Device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring of semiconductor devices, and more particularly, to a method of forming wirings of semiconductor devices suitable for minimizing wiring defects due to heat dissipation effects and hillocks.
    In addition to the nature of transmitting current, the wiring material of the integrated circuit requires various conditions for manufacturing and reliability, such as the efficient manufacture of fine wiring patterns at low cost and the failure of disconnection for long time use. Do.
    Such conditions include low cost, high purity materials, high electrical conductivity, high selectivity with resist, and fine processing. Aluminum (Al), which is known to be most suitable for various conditions as described above, is widely used as a wiring material, and there is a problem such that aluminum is also likely to cause electromigration. In this case, the electromigration, which refers to electrical mobility, is a phenomenon occurring in various metals. In the aluminum wiring layer, which is generally used as a wiring material of a semiconductor device, aluminum ions move due to the flow of electrons when a current is continuously flowed in the aluminum wiring layer for a long time. If this phenomenon persists for a long time, voids or cracks are generated and the wiring layer is disconnected. Therefore, the wiring pattern should be designed so that aluminum is used as the alloy film and the current density of the aluminum alloy film is predicted in advance, so that the current density does not occur.
    Such a method of forming a wiring of a conventional semiconductor device will be described with reference to the accompanying drawings.
    1A to 1D are cross-sectional views of a wiring forming process of a conventional semiconductor device.
    First, as shown in FIG. 1A, a first oxide film 2, a Ti / TiN layer 3, an aluminum layer 4, and a TiN layer 5 are sequentially formed on the front surface of the semiconductor substrate 1. At this time, the Ti / TiN layer 3 and TiN (5) is a high melting point metal (refractory metal) is deposited in the before and after process of the wiring process using a conventional aluminum layer to form a multilayer conductor (electromagnetic migration) (electromigration) minimizes defects.
    As shown in FIG. 1B, after the photoresist film PR is applied onto the TiN layer 5, a wiring line formation region is defined by an exposure and development process to pattern the photoresist film PR.
    As shown in FIG. 1C, the TiN layer 5, the aluminum layer 4, and the Ti / Tin layer 3 are selectively removed by an etching process using the patterned photoresist PR as a mask. 4a). Then, the photoresist film PR is removed.
    As shown in Fig. 1D, a second oxide film 6 is formed on the entire surface of the first oxide film 2 including the wiring line 4a.
    The conventional method for forming a wiring of a semiconductor device has the following problems.
    First, high-melting-point metal is formed only on the upper and lower layers of the aluminum wiring layer, which prevents hillocks from occurring on the side surfaces, and is likely to cause defects due to moisture or impurities in the oxide film or side bonding of the wiring layers. There was a problem.
    Second, because the etching rate between the high melting point metal and the aluminum wiring layer is different in dry etching, the wiring layer is formed in an inverted trapezoidal shape, and thus, the gap gap of the oxide film may not be fully filled after the wiring process, thereby reducing the reliability of the wiring.
    SUMMARY OF THE INVENTION The present invention has been made to solve the problems in the conventional method for forming a wiring of a semiconductor device as described above. In particular, the heat dissipation is increased by increasing the surface area of the wiring line in a wiring layer forming process using a demascene structure. An object of the present invention is to provide a method for forming a wiring of a semiconductor device which can increase the effect and minimize the occurrence of hillock in the wiring layer.
    1A to 1D are cross-sectional views of a wiring forming process of a conventional semiconductor device.
    2A to 2E are cross-sectional views of a wiring forming process of a semiconductor device according to the present invention.
    * Description of the symbols for the main parts of the drawings *
    10 semiconductor substrate 11: first insulating film
    12: trench 13: contact metal
    14 wiring layer 15 antireflection film
    16: second insulating film
    In the method for forming a wiring of a semiconductor device according to the present invention, the method includes forming a first insulating film on a semiconductor substrate, forming a trench having a demesin structure on the first insulating film, and contacting metal on the entire surface of the first insulating film including the trench. And forming an anti-reflection film on the adhesion metal along the trench and the first insulating film surface along the trench and the surface of the first insulating film, and polishing the anti-reflection film, the wiring layer and the adhesion metal to expose the upper surface of the first insulating film. And forming a second insulating film on the entire wiring layer including the first insulating film.
    Such a wiring forming method of the semiconductor device of the present invention will be described with reference to the accompanying drawings.
    2A to 2D are cross-sectional views of a wiring forming process of the semiconductor device of the present invention.
    First, as shown in FIG. 2A, the first insulating film 11 and the photoresist film PR are sequentially formed on the semiconductor substrate 10. Then, the wiring forming region is defined by the exposure and development processes to pattern the photosensitive film PR. In this case, the first insulating film 11 is formed of one of an oxide film and a nitride film.
    As shown in FIG. 2B, a trench 12 is formed by selectively removing the first insulating layer 11 by an etching process using the patterned photoresist PR as a mask. In this case, the upper layer surface of the trench 12 is formed in a round shape. Alternatively, the trench may be formed vertically or slightly sloped. Then, the photoresist film PR is removed.
    As shown in FIG. 2C, the adhesion metal 13 is formed along the surface of the first insulating film 11 including the trench 12. Next, the wiring layer 14 is formed on the entire surface of the contact metal 13. At this time, the adhesion metal 13 is formed of a Ti / TiN layer, the wiring layer 14 is formed of aluminum (Al). In addition, a Ti layer may be formed between the Ti / TiN layer and the wiring layer 14. In addition, the Ti / TiN layer or the aluminum layer is formed using physical vapor deposition (PVD) or chemical vapor deposition (CVD). Subsequently, the wiring layer 14 is reflowed. At this time, the upper layer of the trench 12 is not completely filled. Next, an antireflection film 15 is formed on the wiring layer 14. At this time, the anti-reflection film 15 is formed of TiN.
    As shown in FIG. 2D, the anti-reflection film 15, the wiring layer 14, and the adhesion metal 13 may be chemically polished using a chemical mechanical polishing (CMP) method. Polish until the top surface is exposed. That is, the adhesion metal 13, the wiring layer 14, and the anti-reflection film 15 are polished so as to remain in the trench 12 only.
    As shown in FIG. 2E, a second insulating film 16 is formed on the entire surface of the first insulating film 11 including the metal 13 for contacting the trench 12, the wiring layer 14, and the anti-reflection film 15. In this case, the second insulating layer 16 is formed of one of an oxide film and a nitride film.
    The wiring forming method of the semiconductor device of the present invention has the following effects.
    First, a wiring layer is formed of a multi-layer conductive layer along the surface of the trench of the dimesin structure, so that the exposed surface of the wiring layer is relatively small, so that the possibility of hillock occurrence can be suppressed as much as possible. Less likely to cause defects by combining or suppressing impurities or wiring layers. In addition, complete gap filling of the insulating film is possible after the wiring forming process is completed, thereby improving reliability as wiring.
    Second, since the area of the wiring layer is wider in the same space as compared with the related art, the electro-polation phenomenon can be suppressed to the maximum by reducing the resistance and thermal components generated in the wiring.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] Forming a first insulating film on the semiconductor substrate;
    Forming a trench of a dimesin structure in the first insulating film;
    Forming an adhesion metal on the entire first insulating film including the trench, a wiring layer on the adhesion metal, and an anti-reflection film on the wiring layer along the trench and the first insulating film surface;
    Polishing the anti-reflection film, the wiring layer, and the adhesion metal to expose the upper layer surface of the first insulating film;
    And forming a second insulating film over the entire wiring layer including the first insulating film.
    [2" claim-type="Currently amended] The method of forming a wiring of a semiconductor device according to claim 1, wherein the first and second insulating films are formed of one of an oxide film and a nitride film.
    [3" claim-type="Currently amended] The method of claim 1, wherein the upper layer surface of the trench is formed in a round shape, is formed to be inclined, or is formed vertically.
    [4" claim-type="Currently amended] The method of claim 1, wherein the wiring layer is formed of a metal layer.
    [5" claim-type="Currently amended] The method of forming a wiring of a semiconductor device according to claim 1, wherein the polishing method is a chemical mechanical mirror polishing method.
    [6" claim-type="Currently amended] The method of claim 1, wherein the adhesion metal, the wiring layer, and the anti-reflection film are formed by any one of a physical vapor deposition method and a chemical vapor deposition method.
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    同族专利:
    公开号 | 公开日
    KR100209596B1|1999-07-15|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1996-12-24|Application filed by 문정환, 엘지반도체 주식회사
    1996-12-24|Priority to KR1019960071462A
    1998-09-25|Publication of KR19980052473A
    1999-07-15|Application granted
    1999-07-15|Publication of KR100209596B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019960071462A|KR100209596B1|1996-12-24|1996-12-24|Method for forming an interconnection of semiconductor device|
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